The LED payload panel consists of two boards: one containing 10-20 LED’s arranged in an array of parallel 2-LED strings, the other containing the power conversion and control bus. All components on both boards are thermally linked to thermally conductive, non out-gassing epoxy sandwiched between the two boards. The power regulation bus uses five to ten Linear Technology LED drivers (one per LED string) to boost the battery voltage from 6.6v to the string’s 7.2v. When in a healthy power state and eclipsed by the Earth, the power regulation bus will deliver a 6-amp, 7-volt, high-current bursts to each string of two LEDs. Limited only by battery charge and I2R thermal runaway, the LED power bus can reliably source 200ms bursts once every twenty seconds or thrice rapidly every minute. The ability to deliver these high-current bursts of power is enabled by the unique LiFePO4 battery chemistry being validated in LEO by EQUiSat. The charge/discharge characteristics of these batteries will be recorded on orbit and relayed to ground so their LEO operation can be better understood for future implementation.
EQUiSat’s Command & Data Handling is broken into three parts:
- Electrical Power System (EPS) control
- Data Control
Electrical Power System Control
Power control will be responsible for managing battery charging, and determining battery power consumption. Battery charge management will consist of a power-point tracking algorithm that implements a student-designed PWM switching regulator topology to optimize the net solar panel IV curve. The internal PIC ADC will monitor battery voltage and current (using precision, low-temperature-coefficient sense resistors). For battery validation, LiFePO4 charge/discharge data will be stored in ‘packages’ that include battery current, voltage, and temperature sampled simultaneously and stored in local memory. Each package is encoded using a parity-bit scheme to ensure data fidelity upon downlinking. In addition to eclipse, a healthy battery state serves as a condition for LED flashing and whether data-control can downlink data.
These tasks will be done multiplexed, such that IV calculation will only be done every so often (although no so infrequently that major power is lost), and that priority is given to recording and maintaining battery power levels.
After several iterations of different manufacturers, PIC microcontrollers have been selected for the EQUiSat electronics system. The main criteria were as follows: internal ADC, sufficient on-chip memory, appropriate thermal range, affordability, and a simple C programming interface that is easy to implement and extensible. The selected PIC microcontrollers satisfy each of these requirements monolithically, drastically simplifying system architecture. EQUiSat has minimized necessary on-board data, such that the PIC’s 2Kbytes of on-chip memory can store all critical data for 3 days of operation.
The microcontrollers will be similarly split into the power and data blocks specified above. Although from a system wide design perspective, both subgroups will be logically disjoint, there will be a small limited connection between the two, such that power-control will be able to inform data-control when it can/cannot broadcast information.
The hardware will consist of 8-bit and 16-bit Microchip Technology PIC microcontrollers. Each subgroup will be run by a “main” 16-bit controller which will be handling the core duties of each subgroup unless an unrecoverable error returns, at which point 8-bit backup controllers will power on and take over core duties. The “main” controllers will send keep-alive signals to the backup controllers such that they will only turn on and take over when no keep-alive has been received. Although the 8-bit controllers will be running ostensibly the same code as the 16-bit “main” controllers, there will be changes made to better accommodate the reduced capabilities of the 8-bit controllers (e.g. lower oscillation rate, slower analog to digital conversion speeds, smaller memory, feature difference between 8-bit and 16-bit micros).
Data Control will be responsible for reading ADS and temperature sensor data, transmitting all collected data to ground stations and listening/responding to any kill-transmission signals received from the ground. Data control micros will gather data collected by the power system micros regarding battery temperature/performance and from the attitude determination system sensor suite. The micros will act such that all data is collected from the required sensors as close to synchronously as possible. All data will be recorded in local memory and aggregated. Every two minutes, the data control micros will operate the on-board transmitter downlink this data. Local data memory will be cleared in a queue, such that registers storing the oldest data points are cleared first. The satellite is required to accept a kill signal such that all transmissions can be stopped if they interfere with other satellite’s communications; as such, the data-control micros will be listening for our kill signal via the on-board receiver, should it be needed. If the satellite radio has been turned off due to the kill signal, the micros will continue to record information, storing any overflow data from RAM in local EEPROM.